Unlike conventional random access memory (RAM) chip technologies, in magnetic RAM (MRAM) data is not stored as electric charge, but is instead stored by magnetic polarization of storage elements. The storage elements are formed from two ferromagnetic layers separated by an insulating layer. One of the two layers has at least one pinned magnetic polarization (or fixed layer) set to a particular polarity by an anti-ferromagnetic layer (AFM). The magnetic polarity of the other magnetic layer (or free layer) is altered to represent either a “1” (i.e., anti-parallel polarity) or “0” (i.e., parallel polarity). One such device having a fixed layer, an insulating layer, and a free layer is a magnetic tunnel junction (MTJ). The electrical resistance of an MTJ is dependent on the magnetic polarity of the free layer compared to the magnetic polarity of the fixed layer. A memory device such as MRAM is built from an array of individually addressable MTJs.
FIG. 4A is a block diagram illustrating a spin-torque transfer (STT) magnetic tunnel junction in a low resistance state. A magnetic tunnel junction (MTJ) 400 includes a fixed layer 402 stacked with a tunnel barrier 404 and a free layer 406. A magnetic polarization of the fixed layer 402 is pinned in one direction by an anti-ferromagnetic layer (AFM) (not shown). A magnetic polarization of the free layer 406 is free to change between parallel and anti-parallel states. A resistance of the MTJ 400 depends, in part, on the magnetic polarization of the free layer 406. For example, when the magnetic polarization of the free layer 406 and the fixed layer 402 are substantially aligned, the MTJ 400 has a low resistance. The other stable state of the free layer 406 is examined in FIG. 4B.
FIG. 4B is a block diagram illustrating a spin-torque transfer (STT) magnetic tunnel junction in a high resistance state. For example, the magnetic polarization of the free layer 406 and the magnetic polarization of the fixed layer 402 are in substantially opposite directions. In this case, the MTJ 400 has a high resistance.
MRAM is a non-volatile memory device in which data is stored as a magnetic polarity of the free layer. Read and write speed of MRAM is faster than NAND flash memory. As cell sizes shrink and densities increase, yields and process margin of conventional manufacturing processes decrease, resulting in an increase in cost per die or potential reliability issues with the MRAM. One cause of MRAM failure is electrical shorting between neighboring conductors.
A bottom electrode and a top electrode in an MRAM bitcell can be etched during the same manufacturing process to save costs. After etching the top and bottom electrodes to form individual cells, a dielectric is deposited to fill the space between cells. As cells are spaced closer together to reach higher densities, the aspect ratio of the opening (depth of the opening divided by width of the opening) between cells increases. Dielectric deposition techniques such as chemical vapor deposition (CVD) or physical vapor deposition (PVD) are unable to completely fill large aspect ratio spaces leading to voids in the dielectric layer. If filled with conductive material, the voids may lead to unintentional electrical shorting of conductors later in processing.
The shorting is now described in more detail referencing FIG. 3. FIG. 3 is a top-down view of an array of magnetic tunnel junctions. An array 300 of magnetic tunnel junctions 334 includes top conductors 320 (for example manufactured as trenches). An individual MTJ 334 may be accessed by coupling the top conductor 320 to the desired individual MTJ 334 through top electrodes 332. As discussed above, during manufacturing, voids may form in the dielectric layer between the top electrodes 332 and the top conductors 320. During deposition of the top conductor material, the conducting material may fill the void resulting in a short 340 between top conductors 320. The short 340 may result in failure of the array 300. Thus, manufacturing yield decreases.
Conventionally, the number of shorts 340 are reduced by increasing a height of a top via (not shown) coupled between the top electrode 332 and the top conductor 320. The top via is manufactured taller than the height of the void to prevent overlap of the void and the top conductor 320, preventing the shorts from occurring. The height of the via is defined, in part, by each generation of technology. Because technology is scaled by 70% for each new generation, the height of the via is significantly reduced at each new generation. Process yields may suffer as the shorting issue increases at new generations.